1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, to a semiconductor memory device. More particularly, the invention relates to a reading circuit of a semiconductor memory device, for detecting current flowing in a memory cell to determine a storage state of the memory cell.
2. Description of the Related Art
In a semiconductor memory device, various methods are used to read a storage state of a memory cell. A flash memory as one of nonvolatile semiconductor memory devices will be described as an example. Each memory cell in the flash memory has a memory transistor of a floating gate structure, and the flash memory stores information in accordance with an accumulation amount of charges (electrons) injected into a floating gate of each memory cell. More specifically, in a state where a large amount of electrons are injected into the floating gate, an inversion layer is not easily formed in a channel region, so that a threshold voltage of the memory cell becomes high (defined as a program state). On the other hand, in a state where electrons are discharged from the floating gate, an inversion layer is easily formed in the channel region, so that the threshold voltage of the memory cell becomes low (defined as an erase state). In order to determine whether the state of a selected memory cell is the program state or the erase state at high speed, a reference cell having a threshold voltage which is intermediate between the program state and the erase state is prepared and the threshold voltage is input to a differential input-type sense amplifier.
FIG. 2 shows a basic circuit configuration of such a determination circuit, that is, a reading circuit of a memory cell. The reading circuit shown in FIG. 2 includes a reference cell 204, a selected memory cell 205 which is selected to be read among a plurality of memory cells, a first pre-sense circuit for supplying current from a load circuit 206 to the selected memory cell 205 and outputting a first output voltage according to a storage state of the selected memory cell 205 to a node slsel, a second pre-sense circuit for supplying current from a load circuit 201 to the reference cell 204 and outputting a second output voltage according to a storage state of the reference cell 204 from a node slref, and a sense amplifier 200 for comparing the first output voltage and the second output voltage with each other and determining whether the state of the selected memory cell is a program state or an erase state. The source of the reference cell 204 is grounded, and the drain is connected to the source of an N-type MOSFET 202 as a selection transistor. The drain of the N-type MOSFET 202 is connected to the load circuit 201 and one of inputs of the sense amplifier 200 by the node slref. Similarly, the source of the selected memory cell 205 is grounded and the drain is connected to the source of an N-type MOSFET 203 as a selection transistor. The drain of the N-type MOSFET 203 is connected to the load circuit 206 and the other input of the sense amplifier 200 by the node slsel.
The sense amplifier 200 is constructed by using a known circuit. For example, a current mirror-type sense amplification circuit as shown in FIG. 3 is known. A current mirror is constructed by connecting the gates of P-type MOSFETs P1 and P2 and the drain of P1, the drains of N-type MOSFETs N1 and N2 and the drains of the P-type MOSFETs P1 and P2 are connected to each other, and the sources of the N-type MOSFETs N1 and N2 are connected to the drain of an N-type MOSFET N3. The source of the N-type MOSFET N3 is grounded, and a bias voltage is applied to the gate. By using the current mirror-type sense amplifier having such a configuration, a reading operation is performed by comparing a bit line voltage (second output voltage) of the node slref of a reference cell and a bit line voltage (first output voltage) of the node slsel of a selected cell with each other. It is assumed herein that the threshold voltage of the reference cell 204 is 3 V. In the case where the selected memory cell 205 has a threshold voltage higher than 3 V, the amount of current flowing in the selected memory cell 205 is smaller than the amount of current flowing in the reference cell 204. Consequently, if the resistance characteristic of the load circuit 201 and that of the load circuit 206 are equivalent to each other, the first output voltage is higher than the second output voltage. The voltage difference is amplified by the differential input-type sense amplifier 200, and an L-level (low voltage level) output sdout of the sense amplifier 200 is obtained. On the other hand, in the case where the selected memory cell has the threshold voltage lower than 3 V, the amount of current flowing in the selected memory cell 205 is larger than that of the current flowing in the reference cell 204. Consequently, if the resistance characteristic of the load circuit 201 and that of the load circuit 206 are equivalent to each other, the first output voltage is lower than the second output voltage. The voltage difference is amplified by the differential input-type sense amplifier 200, and the H-level (high voltage level) output sdout of the sense amplifier 200 is obtained. From the viewpoints of uses and chip areas, a number of other circuit configurations of the sense amplifier 200 exist. Although the P-channel current mirror-type sense amplification circuit is shown in FIG. 3, for example, an N-channel current mirror-type sense amplification circuit as disclosed in JP-A 62-008398 (1987) may be used. In this case, it is sufficient to construct a current mirror circuit by N-type MOSFETs and to input a signal to the gate of a P-type MOSFET.
As the capacity of a memory increases, the number of memory cells connected to each bit line increases and, in addition, the bit line length also increases. Consequently, wiring delay caused by increase in an RC constant of parasitic resistance on a bit line and capacitance also increases. In order to solve the problem, a method of minimizing the influence of the parasitic resistance of a bit line and capacitance by introducing a feedback-type bias circuit is employed. The method is disclosed in, for example, JP-A2-285593 (1990) and the like.
FIG. 4 shows an example of the reading circuit using the feedback-type bias circuit. The source of a reference cell 411 is grounded, the drain is connected to the source of an N-type MOSFET 400 and a charging circuit 403 via a selection transistor 404. The source of the N-type MOSFET 400 is connected to an input of an inverter 401, and an output of the inverter 401 is connected to the gate of the N-type MOSFET 400, thereby constructing a feedback type bias circuit 410. Further, the drain of the N-type MOSFET 400 is connected to the sense amplifier 200 and a load circuit 402 by the node slref. The source of a selection memory cell 412 is grounded and the drain is connected to the source of an N-type MOSFET 405 and a charging circuit 408 via a selection transistor 409. The source of the N-type MOSFET 405 is connected to an input of an inverter 406, and an output of the inverter 406 is connected to the gate of the N-type MOSFET 405, thereby constructing a feedback type bias circuit. Further, the drain of the N-type MOSFET 405 is connected to the sense amplifier 200 and a load circuit 407 by the node slsel.
The operation of the reading circuit shown in FIG. 4 will now be described. First, nodes n1 to n4 are charged by the charging circuits 403 and 408. It is desirable to adjust the inversion level of the inverters 401 and 406 so as to cut off the N-type MOSFETs 400 and 405 when Vgs (gate-source voltage) of the N-type MOSFETs 400 and 405 is around a threshold voltage. It is also desirable to set the charging level around the inversion level. As a result, the nodes slsel and slref are separated from the nodes n1 and n3 by the N-type MOSFETs 400 and 405 and are charged to predetermined high voltage levels by the load circuits 407 and 402, respectively. The period of charging by the charging circuits 403 and 408 starts before a word line WL for activating the reference cell 411 and the selection memory cell 412 rises. When the word line WL rises and, after lapse of predetermined time, the charging circuits 403 and 408 are stopped, in the case where the selection memory cell 412 is in an erase state, the voltage of the node n3 drops, and the input level of the inverter 406 becomes the inversion level or less. Therefore, Vgs (gate-source voltage) of the N-type MOSFET 405 becomes the threshold voltage or higher, and an ON state is abruptly obtained. Consequently, the first output voltage of the node slsel drops so as to follow the node n3. On the other hand, when the selected memory cell is in the program state, no current flows from the selected memory cell, so that the voltage of the node n3 does not drop. Therefore, the N-type MOSFET 405 is turned off, so that the node slsel maintains a charging level by the load circuit 407.
However, since the reference cell 411 has the intermediate threshold voltage between the program state and the erase state as described above, the voltage of the node n1 drops though more gently than that of the node n3, and the input level of the inverter 401 becomes the inversion level or less. Consequently, Vgs (gate-source voltage) of the N-type MOSFET 400 becomes the threshold voltage or higher and, though more gently than that of the N-type MOSFET 405, the N-type MOSFET 400 is turned on abruptly. Therefore, the second output voltage of the node slref also once drops so as to follow the node n1.
Therefore, in the case where the selected memory cell 412 is in the erase state, both of the first output voltage at the node slsel and the second output voltage at the node slref drop simultaneously. Finally, the first output voltage drops to a voltage value at which load current of the load circuit 407 and cell current of the selected memory cell 412 in the erase state are equal to each other, the second output voltage drops to a voltage value at which load current of the load circuit 402 and cell current of the reference cell 411 are equal to each other, and a voltage difference occurs between the first and second output voltages. Since drop speeds of the first and second output voltages depend on the load (parasitic resistance and capacitance) of a bit line, reading speed decreases. The effect exhibited by introducing the feedback-type bias circuit is not displayed at all and, instead, an adverse influence is exerted.
It is assumed in the above description that direct-current load circuits are used as the load circuits 402 and 407. Also on assumption that dynamic-type load cells start charging the nodes slsel and slref and also stop the charging circuits 403 and 408, similarly, the charging speeds of the first and second output voltages depend on the load (parasitic resistance and capacitance) of a bit line.
Since a flash memory is a memory in which the threshold voltage of a memory cell can be controlled, a reference voltage (second output voltage) used at the time of reading can be easily generated by freely setting the threshold voltage of a reference cell which is the same memory cell. On the other hand, nonvolatile memories are realized by storing information by changing electric resistance and reading information associated with the changed resistance value, such as MRAM (Magnetic Random Access Memory), OUM (Ovonic Unified Memory) and RRAM (Resistance control nonvolatile Random Access Memory). In such a memory of a variable resistive element-type, it is difficult to generate an intermediate resistance value by one cell, so that a reference cell indicative of an intermediate resistance value is obtained by combined resistance by using four variable resistive elements of bipolar ends. FIG. 5 shows the reference cell. Two sets of resistors, in each of which Rma (program state) of a high electric resistance value and Rmi (erase state) of a low electric resistance value are connected in series, are connected in parallel, thereby generating a reference resistance value of 1 (Rma+Rmi)/2. In this case, however, the reference cell is constructed by including four variable resistive elements and, in contrast, the selected memory cell is constructed by including one variable resistive element. Consequently, a problem occurs such that it is difficult to make the volume loads of the reference cell and the selected memory cell equal to each other. Due to this, wait time occurs until the reference voltage is stabilized. There is consequently the possibility such that reading speed is influenced and, in some cases, a read error is induced.
As described above, when the reference cell having a threshold voltage and a resistance value each of which is intermediate between the program state and the erase state is used, problems occur such that the high-speed reading technique adapted to larger capacity cannot be sufficiently utilized, and it is difficult to make the volume load of the reference cell and that of the selected memory cell equal to each other.